| Giulio Galderisi, Thomas Mikolajick and Jens Trommer Reconfigurable Field Effect Transistors an an Innovative Nanotechnology Platform for Hardware Security Applications
 
 Sahitya Yarragolla and Thomas Mussenbrock
 Compact stochastic modelling of memristive devices for nano-security applications
 
  
 Sajjad Parvin, Frank Sill Torres and Rolf Drechsler
 Toward Optical Probing Resistant Circuits: A Comparison of Logic Styles and Circuit Design Techniques
 
 Andrea Caforio, Fatih Balli and Subhadeep Banik
 The Last SCARE-Frontier: Practical Reverse Engineering of Protected AES-Like Ciphers
 
  
 Mohammad Eslami, Tara Ghasempouri and Samuel Pagliarini
 Reusing the Verification Assertions as Security Checkers for Hardware Trojan Detection
 
 Jonas Ruchti, Danilo Bürger, Nan Du, Michael Pehl and Heidemarie Schmidt
 PUF Key Storage Based on BiFeO3 Memristors
 
  
 Soundes Marzougui, Nils Wisiol, Patrick Gersch, Juliane Krämer and Jean-Pierre Seifert
 Machine-Learning Side-Channel Attacks on the GALACTICS Constant-Time Implementation of BLISS
 
  
 Pierre-Antoine Tissot, Lilian Bossuet and Vincent Grosso
 Fault Resistant Symmetric Encryption Implementation
 
  
 Alexander Treff, Thore Tiemann, Okan Seker and Thomas Eisenbarth
 Extracting machine learning models from IoT ML accelerators via Power and EM attacks
 
  
 Simon Böttger, Florian Frank, Nikolaos Athanasios Anagnostopoulos, Tolga Arul, Stefan Katzenbeisser and Sascha Hermann
 Development of Nanomaterial-Based Physically Unclonable Functions and Dedicated Readout Peripherals
 
 Vincent Ulitzsch, Soundes Marzougui, Mehdi Tibouchi and Jean-Pierre Seifert
 Universal Forgery Attack on Dilithium Leveraging Power Side Channels
 
  
 Animesh Pratap Singh, Elmira Moussavi, Daniyar Kizatov, Dominik Sisejkovic, Xuan Thang Vu, Sven Ingebrandt, Rainer Leupers, Farhad Merchant and Vivek Pachauri
 On the design of genetic analogue keys for biologically logic-locked circuits for Nano-security applications
 
  
 Mateus Simões, Lilian Bossuet, Vincent Grosso, Patrick Haddad, Nicolas Bruneau and Thomas Sarno
 Low Latency Masked Implementation
 
 
 |